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| (R) ISL3084 Data Sheet May 2003 FN5042.3 5GHz VCO The ISL3084 is a 5GHz SiGe monolithic VCO circuit designed to simplify and reduce the cost and size of miniature wireless transceivers. A fully integrated VCO requiring no external elements such as inductors and varactors greatly simplifies low cost local oscillator synthesized applications. Included in this differential design is a low-power standby function and a stable process and temperature biasing operation. The ISL3084 is housed in a 16 lead QFN package well-suited for PCMCIA and miniPCI board applications. Features * Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V * Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 4.9GHz typical * Fully Integrated/No External Varactors or Resonators Required * Isolation Output Buffer/Reduced Load Pulling * Differential Design/Reduced Spurs * Digitally Controlled Power Down Mode * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile Pinout FILTER CAP 2 ISL3084 (QFN) TOP VIEW FILTER CAP 1 Applications * Systems Targeting IEEE802.11b, 11Mbps Standard * Only required VCO function for Intersil PRISM3 chip set * WLAN Applications. GND GND * PCMCIA Wireless Transceivers * TDMA Packet Protocol Radios 12 VCC 16 VTUNE 1 15 14 13 Simplified Block Diagram VCC VCC VCO BIAS VCC OSC+ OSCVTUNE VCC 2 11 OSC+ GND 3 10 OSC- PE GND 4 5 PE 6 VCC 7 GND 8 GND 9 GND GND GND GND Ordering Information PART NUMBER TEMP. RANGE (oC) ISL3084IR ISL3084IR-TK -40 to 85 -40 to 85 PACKAGE 16 Ld QFN Tape and Reel PKG. NO. L16.4x4 Pin Descriptions PIN NUMBER 1 2, 6, 12 5 10 11 15 16 3, 4, 7, 8, 9, 13, 14 Paddle NAME VTUNE VCC PE OSCOSC+ FILTER CAP1 FILTER CAP2 GND N/A DESCRIPTION Input tuning voltage from loop filter. Sensitivity to external injected noise to KVCO. Careful noise-free layout recommended. Supply pins. Requires high quality capacitor RF decoupling. Phase noise behavior proportional to supply pushing specifications. Use good quality, low-frequency decoupling/filtering techniques. Power enable control pin: VCO enabled high. Differential VCO output. Terminate into 100 differential impedance. Terminate one end into 50 when single end output with equivalent loss of power. Use high quality .68F filter capacitor to ground. Use high quality .68F filter capacitor to VCC. Ground Floating paddle. Grounding is recommended. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. PRISM(R) is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc. ISL3084 Absolute Maximum Ratings Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Voltage on Any Other Pin . . . . . . . . . . . . . . . . . . -0.3 to VCC +0.3V VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC For recommended soldering conditions see Tech Brief TB389. Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . .-40o to 85oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. General DC Electrical Specifications PARAMETER Supply Voltage Supply Current @ 3.3V Power Down Supply Current Power Up Time, Filtering dependent Power Down Time CMOS Low-Level Input Voltage CMOS High-Level Input Voltage CMOS High- or Low-Level Input Current TA = 25oC MIN 2.7 0.7*VCC -10 TYP 50 MAX 3.0 20 100 1 0.3*VCC UNITS V mA A s s V V A 10 AC Electrical Specifications PARAMETER RF Frequency Ranges VCC = 2.7 to 3.3V, Vtune operation from 0.5 to 2.2V, TA = 25oC TEST CONDITIONS Vtune = 0.5V Vtune = 1.35V Vtune = 2.2V MIN 5.0 250 65 -9 -3 TYP 4.67 4.92 5.19 40 300 20 70 95 1 1.6 -4 +2 1.8 1.3:1 +10 MAX 4.79 2 350 4 UNITS GHz GHz GHz MHz A MHz/V MHz/V dBc/Hz dBc/Hz dB deg_rms dBm MHz MHz - Tuning Voltage Temperature Coefficient Tuning Pin Input Leakage VCO Gain VCO Gain Temperature Coefficient Phase Noise Vtune = 1.35V, -40 to 85oC Vtune = 2.0V Vtune = 1.35V Vtune = 1.35V, -40 to 85oC Offset 10kHz Offset 100kHz Phase Noise Temperature Coefficient Integrated Phase Noise @ 5GHz. Output Power Supply Pushing Load Pulling Output VSWR Offset @ 10kHz, 0 to 85oC 10kHz to 1MHz Differential into 100 VCC = 2.7V-3.3V, across Vtune range VSWR = 2:1 2:1 BALUM 2 ISL3084 Typical Application 1000P WELL FILTERED VCC 3.9PF .68 .68 FILTER CAP2 FILTER CAP1 GND GND PLL LOOP FILTER VTUNE VCC GND GND GND GND VCC PE VCC OSC+ OSCGND 3.3PF 2:1 LO_OUT BALUM 3.3PF POWER ENABLE 3 ISL3084 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 4 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 4 |
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